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Design of Asynchronous Genetic Circuits

Most digital electronic circuits utilize a timing reference to synchronize the progression of signals and enable sequential memory elements. These designs may not be realizable in biological substrates due to the lack of a reliable high-frequency …

LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits

The increasing integration of analog/mixed-signal (AMS) circuits into system designs has further complicated an already difficult verification problem. Recently, formal verification, which has been successful in the purely digital domain, has made …

A new assertion property language for analog/mixed-signal circuits

In automating the verification of analog/mixed-signal (AMS) circuits, it essential to have a specification language that can describe the behavior that needs to be checked. Although powerful and very expressive, many such languages have a steep …

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets

Mixed-signal designs integrate digital and analog circuits which complicates the already difficult verification problem. This paper presents a model, labeled hybrid Petri nets (LHPNs), that is developed to model this heterogeneous set of components. …

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized …

ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation

In this paper, we propose a new scheduling method for asynchronous circuits in bundled-data implementation. The method is based on integer linear programming (ILP) which explores an optimum schedule under resource or time constraints. To schedule …

Modular verification of timed circuits using automatic abstraction

The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into …

Synchronous interlocked pipelines

Locality principles are becoming paramount in controlling advancement of data through pipelined systems. Achieving fine grained power down and progressive pipeline stalls at the local stage level is therefore becoming increasingly, important to …

A standard-cell self-timed multiplier for energy and area critical synchronous systems

This paper describes the design of a standard-cell self-timed multiplier for use in energy and area critical synchronous systems. The area of this multiplier is bounded by N rather than N/sup 2/ as seen in more traditional combinational parallel …

Interfacing synchronous and asynchronous modules within a high-speed pipeline

This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of …