Scott Little is an expert in analog and mixed-signal (AMS) design and verification tools, flows, and methodologies (TFM). He has a wide range of experience including behavioral modeling, AMS verification, and tool support and development. He is a recognized leader evidenced by leading AMS verification TFM development at Intel and Freescale as well as chairing the SystemVerilog-AMS and SV-DC (nettypes) standards committees.

Scott Little completed his PhD at the University of Utah in 2008. He developed a labeled hybrid Petri net (LHPN) model for AMS systems, extended difference bound matrix (DBM) based verification algorithms to HPN models, implemented DBM-based algorithms in LHPN Embedded/Mixed-signal Analyzer (LEMA) tool, and devised algorithms to generate LHPN, Verilog-AMS, and VHDL-AMS models from simulation data.• Developed a labeled hybrid Petri net (LHPN) model for AMS systems.